PTL 1 describes one example of an accelerator control apparatus. As illustrated in FIG. 10, the accelerator control apparatus described in PTL 1 includes an information processing apparatus 8. The information processing apparatus 8 includes a shared memory 81 and a plurality of accelerators 821 to 823 connected to the shared memory 81.
The shared memory 81 stores data to be processed by the accelerators 821 to 823. The accelerators 821 to 823 process data transferred from the shared memory 81 to the accelerators 821 to 823. The accelerators 821 to 823 transfer again the processed data to the shared memory 81. The transfer and processing of data are repeated until a desired process is completed.